A computing system comprising capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit.

A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers.

A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU.

The PE structure for integer arithmetic forms an FP-RA supporting FP arithmetic, and PEs are paired to form a floating point unit (FPU)-PE.

A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa.

The floating-point unit may execute the same floating-point instruction stream twice.