The invention concerns, in particular, the processing of interruptions in an autonomous peripheral controller for a multiprocessor computer system.
Shared program function blocks are allocated among a plurality of jobs running on a plurality of processor nodes (32-37) in a multiprocessor computer system.
A distributed shared memory multiprocessor computer system utilizes page placement policies to reduce data access latencies.
A multiprocessor computer system includes processing element nodes interconnected by physical communication links.
An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing.
A symmetric multiprocessing fault-tolerant computer system may use duplication or continuous replay.
An interrupt controller efficiently manages execution of tasks by a multiprocessor computing system.
A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space.
In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources.
A flowchart and circuit for tracking memory page accesses in a multi-processor computing system to optimize memory bandwidth utilization.
A method and apparatus for managing coherence between two processors (12, 14) of a two processor node (10) of a multi-processor computer system.
To do so, virtual page structures are created, where the virtual page structures reflect physical page access privileges to shared memory for processors in a symmetric multiprocessing computer system.
The optimal number (n) is determined based, at least in part on N, B and S. The system and method are implementable in a multithreaded, multi-processor computing system.
An apparatus, method, and program product for optimizing a multiprocessor computing system by sampling memory reference latencies and adjusting components of the system in response thereto.