According to the invention, a first instruction word (IW1) and a second instruction word (IW2) are used.
By means of the first characteristic contained in the program word a secondary instruction word is generated by exchanging the instruction word parts contained in the program word with those in a preceding secondary instruction word.
The second instruction word corresponds to a second instruction set, wherein the second instruction word encodes at least one instruction to be executed by a single issue slot.
The first instruction word corresponds to a first instruction set, wherein the first instruction word encodes a plurality of instructions to be executed in parallel by the plurality of issue slots.
The fetch stage is provided with a word buffer (62) that stores both a current instruction word and a next instruction word.
An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories.
The invention relates to a method for recognising a correct command entry address, according to which each command word has a predetermined start bit code, which indicates the length of said word.
On the system side the aim of the invention is solved by providing for the instruction word buffer to consists of a memory with optional line-by-line access.
A very long instruction word (VLIW) architecture describes a processor comprising multiple functional units operating in parallel.
Thus, an instruction word may contain a greater number of issue slots than there are functional units.