The unclocked logic can include a delay line.
The FULL Flag resets the clock multiplexer to provide the delay line with the retimed clock, and also switches the delay line to read the retimed data at the retime clock rate.
The cell (1) comprises a data circulation output (3) and a calculation output (4), as well as a main delay line (5) and an auxiliary delay line (6) in parallel.
The resultant optical waveform is transmitted to a predetermined delay line to provide an electrical output from the predetermined delay line corresponding to a main lobe of the resultant optical wavefront.
A sound synthesis system employs a variable-length delay line (154) whose length is modulated at a frequency that is close to the fundamental frequency of the delay line.
Line delay (23), together with field delay memories (22, 24), provide the interlaced line above and below the current line for the comb filter.
Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset.
A self-oscillating remote sensor device includes a delay-line sensor system having at least one delay-line and at least one sensor element.
A data retiming arrangement applies data to be retimed to a delay line.
A first transducer is acoustically coupled to the tapped-delay-line.
A second transducer is acoustically coupled to the tapped-delay-line.
Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements (685, 690).
A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells.
Each delay line imposes a phase delay relative to its length on a signal passing therethrough.